EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0GLB fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin O 0:2 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk 1GLB fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin O 0:2 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn 2GLB fpga_0_DDR_CLK_FB_OUT O 1 ddr_clk_feedback_out_s 3A fpga_0_Audio_Codec_Bit_Clk_pin I 1 fpga_0_Audio_Codec_Bit_Clk 4A fpga_0_Audio_Codec_SData_In_pin I 1 fpga_0_Audio_Codec_SData_In 5A fpga_0_Audio_Codec_AC97Reset_n_pin O 1 fpga_0_Audio_Codec_AC97Reset_n 6A fpga_0_Audio_Codec_SData_Out_pin O 1 fpga_0_Audio_Codec_SData_Out 7A fpga_0_Audio_Codec_Sync_pin O 1 fpga_0_Audio_Codec_Sync 8B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin IO 0:7 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS 9B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin IO 0:63 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ 10B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin O 0:12 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr 11B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin O 0:1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr 12B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn 13B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE 14B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn 15B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin O 0:7 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM 16B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn 17B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn 18C fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin IO 1 fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk 19C fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin IO 1 fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data 20C fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin IO 1 fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk 21C fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin IO 1 fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data				# NAME DIR [LSB:MSB] SIG ATTRIBUTES 22D fpga_0_PushButtons_5Bit_GPIO_IO_pin IO 0:4 fpga_0_PushButtons_5Bit_GPIO_IO 23E fpga_0_RS232_Uart_1_ctsN_pin I 1 fpga_0_RS232_Uart_1_ctsN 24E fpga_0_RS232_Uart_1_sin_pin I 1 fpga_0_RS232_Uart_1_sin 25E fpga_0_RS232_Uart_1_rtsN_pin O 1 fpga_0_RS232_Uart_1_rtsN 26E fpga_0_RS232_Uart_1_sout_pin O 1 fpga_0_RS232_Uart_1_sout 27F fpga_0_SysACE_CompactFlash_SysACE_CLK_pin I 1 fpga_0_SysACE_CompactFlash_SysACE_CLK 28F fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin I 1 fpga_0_SysACE_CompactFlash_SysACE_MPIRQ 29F fpga_0_SysACE_CompactFlash_SysACE_MPD_pin IO 0:15 fpga_0_SysACE_CompactFlash_SysACE_MPD 30F fpga_0_SysACE_CompactFlash_SysACE_CEN_pin O 1 fpga_0_SysACE_CompactFlash_SysACE_CEN 31F fpga_0_SysACE_CompactFlash_SysACE_MPA_pin O 0:6 fpga_0_SysACE_CompactFlash_SysACE_MPA 32F fpga_0_SysACE_CompactFlash_SysACE_OEN_pin O 1 fpga_0_SysACE_CompactFlash_SysACE_OEN 33F fpga_0_SysACE_CompactFlash_SysACE_WEN_pin O 1 fpga_0_SysACE_CompactFlash_SysACE_WEN 34G fpga_0_VGA_FrameBuffer_TFT_LCD_BLNK_pin O 1 fpga_0_VGA_FrameBuffer_TFT_LCD_BLNK 35G fpga_0_VGA_FrameBuffer_TFT_LCD_B_pin O 0:5 fpga_0_VGA_FrameBuffer_TFT_LCD_B 36G fpga_0_VGA_FrameBuffer_TFT_LCD_CLK_pin O 1 fpga_0_VGA_FrameBuffer_TFT_LCD_CLK 37G fpga_0_VGA_FrameBuffer_TFT_LCD_G_pin O 0:5 fpga_0_VGA_FrameBuffer_TFT_LCD_G 38G fpga_0_VGA_FrameBuffer_TFT_LCD_HSYNC_pin O 1 fpga_0_VGA_FrameBuffer_TFT_LCD_HSYNC 39G fpga_0_VGA_FrameBuffer_TFT_LCD_R_pin O 0:5 fpga_0_VGA_FrameBuffer_TFT_LCD_R 40G fpga_0_VGA_FrameBuffer_TFT_LCD_VSYNC_pin O 1 fpga_0_VGA_FrameBuffer_TFT_LCD_VSYNC 41H sys_clk_pin I 1 dcm_clk_s 42I fpga_0_DDR_CLK_FB I 1 ddr_feedback_s 43J sys_rst_pin I 1 sys_rst_s